Abstract

Exponential growth in global computing demand is further exacerbated by the high energy requirements of conventional architectures, which are dominated by costly data movement requirements. In-memory computing with Resistive Random Access Memory (RRAM) addresses this challenge by co-integrating memory and processing, but faces tremendous hurdles related to device-level non-idealities and offers poor scalability in large computing tasks. Here, we introduce MELISO+ (In-Memory Linear Solver), a full-stack, distributed framework for energy-efficient in-memory computing. MELISO+ proposes a novel two-tier error correction mechanism to mitigate device non-idealities, and develops a distributed RRAM computing framework to enable matrix computations exceeding dimensions of 65,000×65,000. This approach reduces first- and second-order arithmetic errors due to device non-idealities by over 90\%, enhances energy efficiency by three to five orders of magnitude, and decreases latency 100-fold. Hence, MELISO+ allows lower-precision RRAM devices to outperform high-precision device alternatives in accuracy, energy and latency metrics. By unifying algorithm-hardware co-design with scalable architecture, MELISO+ considerably advances sustainable, high-dimensional computing suitable for applications like large language models and generative artificial intelligence.

Contents

The contents of this article can be accessed here:

• arXiv.
• Nature Communications Engineering: pending.